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From: mslater@cup.portal.com (Michael Z Slater)
Newsgroups: comp.arch
Subject: Re: SPARC implementation or architecture
Message-ID: <41377@cup.portal.com>
Date: 18 Apr 91 01:50:06 GMT
References: <1991Apr17.183822.7681@elroy.jpl.nasa.gov>
Organization: The Portal System (TM)
Lines: 23

David Robinson writes:

>Has anyone compared why SPARC tends to run slower at the same clock
>speed as other RISC chips?  Will this be a factor as the clock rate
>is cranked up to 100Mhz and beyond?

I think the primary reason SPARC provide less performance at a given clock
speed is that they have a single instruction/data bus between the processor
and the cache, which puts a bubble in the pipe every time a load or store
occurs. Future implementations will have separate on-chip instruction and
data caches, and this limitation will go away.

So no, I don't think this will be a factor as the clock rate is cranked up,
because this will happen on new implementations.

There is an interesting paper in the ASPLOS-IV proceedings that compares the
MIPS and SPARC architecture and claims that SPARC actually executes
significantly fewer instructions for a given set of benchmarks (SPEC).
This would imply that it does not have an architectural disadvantage.

Does anyone who is familiar with that paper have any comments on it?

Michael Slater, Microprocessor Report  mslater@cup.portal.com