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From: preston@ariel.rice.edu (Preston Briggs)
Newsgroups: comp.arch
Subject: Re: SPARC implementation or architecture
Message-ID: <1991Apr18.142341.23097@rice.edu>
Date: 18 Apr 91 14:23:41 GMT
References: <1991Apr17.183822.7681@elroy.jpl.nasa.gov> <41377@cup.portal.com>
Sender: news@rice.edu (News)
Organization: Rice University, Houston
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>David Robinson writes:
>>Has anyone compared why SPARC tends to run slower at the same clock
>>speed as other RISC chips?  Will this be a factor as the clock rate
>>is cranked up to 100Mhz and beyond?

mslater@cup.portal.com (Michael Z Slater) writes:
...
>There is an interesting paper in the ASPLOS-IV proceedings that compares the
>MIPS and SPARC architecture and claims that SPARC actually executes
>significantly fewer instructions for a given set of benchmarks (SPEC).
...
>Does anyone who is familiar with that paper have any comments on it?

The paper is

	An Analysis of MIPS and SPARC Instruction Set Utilization on
	the SPEC Benchmarks
	Cmelik, King, Ditzel, Kelly
	ASPLOS-IV, 1991

It was presented by Dave Ditzel, of Sun Microsystems.
First off, people should read the paper; it's pretty hard to summarize
a summary of a big study!  Nevertheless, here's the raw instruction
counts:

	Benchmark		MIPS		SPARC		M/S
	------------------------------------------------------------
	spice		   21,569,202,673   22,878,017,309	0.94
	doduc		    1,613,227,089    1,303,276,485      1.24
	nasa7		    9,256,812,144    6,614,656,686	1.40
	matrix300	    2,775,967,947    1,693,589,255	1.64
	fppppppp	    2,316,200,144    1,443,008,199	1.61
	tomcat		    1,812,691,974    1,626,342,454	1.11
	------------------------------------------------------------
	FP Geometric Mean					1.30
	------------------------------------------------------------
	gcc		    1,110,816,041    1,115,986,011	0.96
	expresso	    2,828,804,443    2,930,860,108	0.97
	li		    6,022,855,076    4,661,320,853	1.29
	eqntott		    1,243,469,361    1,321,536,444	0.94
	------------------------------------------------------------
	Integer Geometeric Mean					1.03
	------------------------------------------------------------
	Overall Geometric Mean					1.18

Basically, the MIPS executed more instructions, except on most of the integer
benchmarks.  The authors note that a fairer comparison, taking into
account register window overhead, interlocks, and annulled instructions
still gives a 9% advantage to the SPARC.

The biggest contributer to the difference seemed to be that the
MIPS required two instructions to load or store a DP floating-point value.
Hence the wide disparity in the FP benchmarks.

Someone (Charlie Price?) from MIPS objected that the study had been carried
out with an old generation of the MIPS compilers, and that newer numbers
were significantly better for the MIPS.  Ditzel admitted this was possible,
but noted that they had used what was available on the market when they did
the study.

The paper goes on to discuss the affect of libraries, load/store usage,
branches, nops, integer ops, and fp ops.  Lots of good ideas for
both architectures.  The appendix contains detailed numbers for each
of the benchmarks.

BTW, the numbers were collected with pixie (mips) and spixie (sparc).
One the consistantly interesting parts of the conference is the methodology
used to perform experiments.  Lots of good ideas here.

Preston Briggs