Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!usc!isi.edu!rod From: rod@isi.edu (Rodney Doyle Van Meter III) Newsgroups: comp.arch Subject: Re: Adding fire to the segmentation flamefest... Keywords: segments: do they really suck? Message-ID: <17629@venera.isi.edu> Date: 18 Apr 91 17:02:31 GMT References: <9234@lkbreth.foretune.co.jp> <45180@super.ORG> <9244@lkbreth.foretune.co.jp> <2275@cluster.cs.su.oz.au> Reply-To: rod@venera.isi.edu (Rodney Doyle Van Meter III) Distribution: comp Organization: Information Sciences Institute, Univ. of So. California Lines: 29 I came in late on this discussion, so forgive me if if this has been mentioned. I don't know what became of it, but in 1984 Jim Kajiya and William Dally of Caltech proposed a segmented architecture with floating point addresses. The exponent determines where in the remaining bits the division between segment number and offset into the segment occurs. The exponent is also considered to be part of the segment number, so an exponent of 1 and segment fraction of 0 is different from an exponent of 2 and a segment fraction of 0. They give as an example MULTICS addressing. MULTICS had 36-bit addresses partitioned as an 18-bit segment number and an 18-bit offset. This is awkward if you want segments bigger than a quarter meg, or if you need more than a quarter million segments. With their architecture, 5 bits out of 36 would be the exponent, indicating how the other 31 bits are partitioned between segment and exponent. This gives the ability to address up to 8 billion segments, and segments can be up to 2 billion words long. This work of theirs was part of a proposed object-oriented machine. They expecet one segment per object. Access between segments will have to be very fast, unlike some other machines. Check out Caltech Technical Report 5168:TR:84 if you're interested. --Rod