Newsgroups: comp.arch
Path: utzoo!henry
From: henry@zoo.toronto.edu (Henry Spencer)
Subject: Re: RISC vs CISC (very long)
Message-ID: <1991Apr18.195534.10505@zoo.toronto.edu>
Date: Thu, 18 Apr 1991 19:55:34 GMT
References: <1991Apr03.232400.1560@kithrup.COM> <1991Apr7.064855.25469@zoo.toronto.edu> <537@appserv.Eng.Sun.COM> <2419@spim.mips.COM>
Organization: U of Toronto Zoology

In article <2419@spim.mips.COM> mash@mips.com (John Mashey) writes:
>-A1 [29k] is slightly unusual in having more integer registers, and less FP
>than usual. ...
>-D1 [88k] is unusual in sharing integer and FP registers

This is slightly out of date.  AMD appears to have (wisely) decided to ditch
the peculiar 29027 FPU architecture.  The 29050's on-chip floating point uses
the integer register bank (disregarding one or two odd instructions), subject
to a constraint that double-precision arithmetic use even-odd pairs.
-- 
And the bean-counter replied,           | Henry Spencer @ U of Toronto Zoology
"beans are more important".             |  henry@zoo.toronto.edu  utzoo!henry