Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!swrinde!sdd.hp.com!mips!mash From: mash@mips.com (John Mashey) Newsgroups: comp.arch Subject: Re: RISC vs CISC Message-ID: <2457@spim.mips.COM> Date: 18 Apr 91 23:24:36 GMT References: <537@appserv.Eng.Sun.COM> <2419@spim.mips.COM> <11810@exodus.Eng.Sun.COM> Sender: news@mips.COM Organization: MIPS Computer Systems, Inc. Lines: 45 Nntp-Posting-Host: winchester.mips.com In article <11810@exodus.Eng.Sun.COM> chased@rbbb.Eng.Sun.COM (David Chase) writes: >Hey, you left out the Acorn Risc Machine. Not a big name in the >workstation market, but I understand that they sell a good number of >them, and the instruction set is "interesting" (a bit-twiddler/ >superoptimizer's wet dream, if you ask me, but probably "risc" by many >definitions of the term). VTI sells this chip in the US, they should >be able to give you a spec if you want it. Sorry, it could have been included, but I just ran out of time and space, and I thought I had enough data to make the point, which was that there were noticable differences between RISC and CISC architectures, regardless of the implementation. The ARM would certainly get classified as a RISC, with 32-bit instructions, 1 size a handful of memory address modes no indirect addressing only loads/sotres access memory no more than 1 memory address/instruction alignment (I think) 1 use of memory control/TLB per instruction for data 4 bits available for integer register specifiers The manual I have shows it with no FP at all, but then it's 2 years' old. Although I didn't post them, the more complete tables that I was working from contained multiple implementations of some of the architecture families, from which one may find several trends: a) Only occasionally does anyone (RISC or CISC) subtract instructions. b) Both RISC and CISC often add instructions as time goes on. c) Sometimes CISCs got CISCier in their ISAs, i.e. ,by adding addressing modes the way the 68020 did, or by deleting alignment characteristics the way 360->370 did. d) Sometimes CISC implementations were done in more RISC-like fashion (i.e., trap certain opcodes and emulate)> e) I could find no architecture that clearly started as a RISC, and then seriously evolved into a CISC, or took on any of the attributes that I used to distinguish CISCs and RISCs. (So much for this idea that CRISP = Complex RIS Processor (not AT&T CRISP) is a merger of RISC and CISC, and that current RISC and CISC architectures are evolving towards each other. Nonsense.) -- -john mashey DISCLAIMER: UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems MS 1/05, 930 E. Arques, Sunnyvale, CA 94086