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From: mark@acorn.co.uk (Mark Taunton)
Newsgroups: comp.sys.acorn
Subject: Proposed ARM enhancements (was Re: Memory handling)
Message-ID: <6442@acorn.co.uk>
Date: 17 Apr 91 11:40:29 GMT
References: <1991Mar20.143227.247@ecc.tased.oz.au> <1991Mar22.171119.11147@ifi.uio.no> <6079@acorn.co.uk> <4826@syma.sussex.ac.uk>
Reply-To: mark@acorn.co.uk (Mark Taunton)
Organization: Acorn Computers Ltd, Cambridge, UK
Lines: 62

In article <4826@syma.sussex.ac.uk> gavinw@syma.sussex.ac.uk writes:
>Two enhancements to future ARMs that I would like to see are
>
>i) 'modify offset-register' writeback addressing-modes
>ii) trap register-values-outside-given-range to speed up range
>checking.

Just to remind people, the R in ARM stands for RISC (I won't raise the
issue of what the A stands for these days :-|), and RISC, at least by
most commonly-encountered definitions stands for "Reduced Instruction
Set Computer/Computers/Computing/Complexity/C<whatever>".  I fear that
the second proposed "enhancement" doesn't really fall into this
category, (in terms of the original basis of RISC processor design)
although I accept that it can still be useful.  However if you need to
do range-checking on a constant range, perhaps the following may help.
The "obvious" direct coding for range checks on signed quantities is
(in RISC iX assembler syntax):

	cmp	rx, #lower_bound	@ x < lower_bound ?
	swilt	SWI_range_error
	cmp	rx, #upper_bound	@ x > upper bound ?
	swigt	SWI_range_error

[I have assumed you really do want a "trap", so have used a
conditional SWI above - you can implement the SWI handling yourself
under either RISC OS or RISC iX.  Alternatively, a simple Bcc (or, to
allow diagnosis assuming the calling routine will not continue or has
saved r14, a BLcc) to suitable handler code might be used instead.]

OK, that's 4 instructions (perhaps more, if lower_bound or upper bound
can't be represented as an ARM immediate field, or they're not already
in a pair of registers).  If lower_bound is actually 0, switching to
unsigned working helps a lot:

	cmp	rx, #upper_bound	@ (unsigned)x > upper_bound ?
	swihi	SWI_range_error	

This can also be adjusted for the unlikely possibility of lower_bound
-ve, upper bound 0.

Even for the general case (neither bound 0), assuming there is a spare
register around, you can still get it down by one instruction by
treating things as unsigned:

	sub	rtemp, rx, #lower_bound
	cmp	rtemp, #upper_bound-lower_bound
	swihi	SWI_range_error

or if the particular constant values work out better:

	cmp	rx, #upper_bound {r_upper_bound}
	rsble	rtemp, rx, #lower_bound {r_lower_bound}
	swigt	SWI_range_error

(We need to use rsb and a temporary since ARM has no reverse compare
instruction.)

On the second idea ('modify offset-register' writeback addressing-modes) 
I am not at all clear what is meant. Can you elaborate?


Mark Taunton, Acorn Computers Ltd.		mark@acorn.co.uk