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From: livio@alessia.dei.unipd.it (Livio Plos)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: 14Mhz Hack
Summary: My hack
Message-ID: <10492@alessia.dei.unipd.it>
Date: 15 Apr 91 17:47:21 GMT
References: <1991Apr12.182537.1835@lynx.CS.ORST.EDU>
Organization: DEI Padova University
Lines: 60

In article <1991Apr12.182537.1835@lynx.CS.ORST.EDU>, rudolpe@jacobs.CS.ORST.EDU (Eric Hans Rudolph) writes:
> 
> Is there anyone out there who can tell me just how long I can hold off Dtack*
> and where I can have it asserted, assuming that the 14Mhz 68k starts the
> bus cycle S0 at the same time it WOULD have if it were running at 7Mhz?
> (is this a valid assumption? I am XORing CDAC (not inverted) with 7Mhz. )
> 
> Is it possible to get this hack to work?
> 
> If I divide down the 1.4Mhz Eclock by 2 with a flip flop, the new E clock
> will be at a 50/50 duty cycle, assuming I can get VPA* and VMA* to work,
> does the 50/50 pose a problem?
> 
No problem, I suppose, because 8520 are built to work with processor that give
them a 50% duty cycle clock, but they are so good that work also with a 60/40.

> Any comments? I am desperate...
> 
> rudolpe@jacobs.cs.orst.edu

These are the timings of my hack.

	           t1          t2 t3 t4 t5 t6
		   |           |   | |   | |	
		s2    s3    s4    s5    s6    s7
	      _____       _____       _____       _____
7M	_____|     |_____|     |_____|     |_____|     |_____

	 __    __    __    __    __    __    __    __    __
14M        |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__

       ___________                           _____________
AS*	\\\\\\\\\\\_________________________/////

	___________                          __________
ASD*               |________________________/////

	_____________________		     ___________
DTACK*	            \\\\\\\\\\______________/////

           ____________________              ___________
DTACKout*                      \____________/////


These are the timings. With U2b I delay the sample of the dtack* until
t2 because U2b-Q goes low only after t1 and release the U2a on the falling
edge of s4 (t2). Here it samples dtack,as 68k do, and gives it availble to
the 68K-14 that takes it in t3 and in t5 68k-14 read data on the data bus.
In the technical reference I read that data isn't availble before 50nS of t6
so I must stay in this window, between t5 and t6 there are less than 30nS.

Please pause the buliding of the New14Accel, because there is a problem 
with a delay of U4d or use inverter instead of U4b-c-d.
I'm fixing it to use it with only 4 ic and the 68k/16.

I'll post the new release.

				Livio

P.S.:excuse me for my bad English.