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From: fillmore@SUN2.EMR.CA (Bob Fillmore)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: Amiga Custom Chips
Message-ID: <9104172234.AA04604@sun2.emr.ca>
Date: 17 Apr 91 22:34:00 GMT
Sender: daemon@ucbvax.BERKELEY.EDU
Lines: 34

In article <20298@cbmvax.commodore.com> daveh@cbmvax.commodore.com (Dave Haynie) writes:
>
>Specific to the Amiga, there were several problems.  First of all, the video
>chips are directly tied to video.  If you speed up the bus cycle, you speed
>up the video shift rate, unless you go to a multiple of it.  The current Agnus
>runs a 280ns cycle.  To double that, and go to 140ns, you would need 60ns
>DRAM, which are only now becoming available in large quantities, and are still
>quite expensive (though, if they're on schedule, they'll get cheap in the next
>year or so).  Any somewhat faster bus speedup and you lose NTSC or VGA scan
>and pixel rates.  While it's conceivable that you could divorce the scan
>rate from the bus rate, that's a MAJOR architectural change, far more complex
>than building new chips that speed up in other ways (32 bit bus is the way
>the microprocessors gained their modern speed, more than clock rate speedups).
>
>-- 
>Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests"
>   {uunet|pyramid|rutgers}!cbmvax!daveh      PLINK: hazy     BIX: hazy
>      "That's me in the corner, that's me in the spotlight" -R.E.M.

A question I have been meaning to ask for a while:
How hard would it be to implement phased memory banks in the Amiga,
a technique used by mainframe manufacturers to implement fast memory
by using slow DRAM chips?

Phased memory banks work by using the low-order bits of the address
as a bank select so that the address bus cycle can be faster than
the memory bank cycle.


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Bob Fillmore, Systems Software & Communications    email: fillmore@emr1.emr.ca
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