Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!bridge2!jarthur!nntp-server.caltech.edu!toddpw
From: toddpw@nntp-server.caltech.edu (Todd P. Whitesel)
Newsgroups: comp.sys.apple2
Subject: Re: Speed Loss
Message-ID: <1991Apr16.095734.22040@nntp-server.caltech.edu>
Date: 16 Apr 91 09:57:34 GMT
References: <1991Apr16.072826.7806@cs.uow.edu.au>
Organization: California Institute of Technology, Pasadena
Lines: 32

u9050728@cs.uow.edu.au (Shane Kelvin Richards) writes:

>	Its interesting to note that the Apple //GS Hardware reference says
>that although the mhz of the GS is 2.8, it actually is only about 2.5
>apparently to service all the other things going on. I wonder what the .3
>mhz is being used for?

DRAM refresh. The reason why DRAMs are so cheap is that they aren't really
memories -- if you just give them power but do nothing else they will
forget everything after ten milliseconds or so (most DRAMs are spec'd to
retain for at least 6 or 8 ms). In order to make them remember, you have to
tweak them every so often so that each row of cells in the square array
on the chip gets accessed at least once every 6 or 8 ms (or whatever the
retention spec is). This is done regularly as you access the memory, but
only to the rows you're actually using -- you have to make sure the others
get refreshed too and that takes an overhead bite out of the memory system.

Whenever the GS is in fast mode, the CPU is suspended every 10th cycle and
a refresh is performed. That's where the other .3 mhz goes. The actual
numbers are

	14.31818 mhz / 5 cycles = 2.863636 mhz maximum

	2.863636 mhz * 90% used by CPU = 2.57727 mhz average

if no accesses to the slow side of the machine are made. Then things
get really bizarre, and Apple hasn't really documented them (I think
they're ashamed to describe how truly brain-dead the original FPI refresh
circuit was).

Todd Whitesel
toddpw @ tybalt.caltech.edu