Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!sol.ctr.columbia.edu!emory!hubcap!ddyer
From: ddyer@hubcap.clemson.edu (Doug)
Newsgroups: comp.sys.m68k
Subject: Re: need explanation on 68040 cache
Keywords: DMEMC, 68040, motorola, cache
Message-ID: <1991Apr16.012650.21130@hubcap.clemson.edu>
Date: 16 Apr 91 01:26:50 GMT
References: <1991Apr16.003827.18339@hubcap.clemson.edu>
Distribution: comp.arch
Organization: Clemson University
Lines: 11

ddyer@hubcap.clemson.edu (Doug) writes:

>	   The cache is 32 bits (lw) with a dirty bit for each lw, which
	        ^^^^^^^^^^^^^^^
>	   seems that only a lw may be accessed, but 4 bits (3-0) can
>	   access 16 bytes - the line length. Does the IU know what to

I meant to say "The cache LINE is 4 32-bit long words". 

-- 
 Doug Dyer        ddyer@hubcap.clemson.edu