Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!elroy.jpl.nasa.gov!swrinde!mips!rogerk From: rogerk@mips.com (Roger B.A. Klorese) Newsgroups: comp.sys.mips Subject: Re: MIPS-I cf. MIPS-II Message-ID: <2315@spim.mips.COM> Date: 16 Apr 91 18:35:59 GMT References: <2234@spim.mips.COM> <2242@spim.mips.COM> <1991Apr16.173023.7070@aero.org> Sender: news@mips.COM Organization: MIPS Computer Systems, Sunnyvale, California Lines: 23 Nntp-Posting-Host: servitude.mips.com In article <1991Apr16.173023.7070@aero.org> jordan@aero.org (Larry M. Jordan) writes: >Could someone summarize the basic distinction between these >two generations? I've not seen these terms used before (I've >not much exposure to this news group). Which versions of >MIPS OS correspond? MIPS-I: R2000, R3000, R3000A (modulo the RE, reverse-endian, bit in the Status Register). Documented in the "MIPS RISC Architecture" book currently available. MIPS-II: R6000. Full superset of MIPS-I; adds Load Linked/Store Conditional, Branch (on xxx) Likely, Exception instructions (Trap if xxx), Load/Store Double Coprocessor, Flush, Invalidate, Store to/Load from Cache. These are all 32-bit instructions. It would not take a great leap to interpret the technology announcement for the R4000 to assume that a 64-bit superset is coming. -- ROGER B.A. KLORESE MIPS Computer Systems, Inc. MS 6-05 930 DeGuigne Dr. Sunnyvale, CA 94088 +1 408 524-7421 "10 years of Reagan/Bush have brought us to a new place: postconstitutional America." - Jon Carroll rogerk@mips.COM | {ames,decwrl,pyramid}!mips!rogerk