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From: doug@eris.berkeley.edu (Doug Merritt)
Newsgroups: comp.sys.next
Subject: Re: RISC vs. CISC -- SPECmarks
Message-ID: <1991Apr15.165540.14270@agate.berkeley.edu>
Date: 15 Apr 91 16:55:40 GMT
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In article <1991Apr10.155032.14786@data.com> smb@data.com (Steven M. Boker) writes:
>
>Did anyone notice the graphic on the front page of the New York Times
>Business section that put NeXT in the 88000 camp with a little asterisk
>that noted "expected".  I wonder what their sources are?

The San Jose Mercury said rather offhandedly last week that NeXT will be
coming out with an 88000 system in the fall in the $8K to $10K range.
More precisely they said it would be based on a new member of the 88K
family that Motorola hasn't released yet; I've forgotten the model number.
This was in the context of relating a talk Steve Jobs gave where he
announced that 8000 systems were shipped in the first quarter, so they
sort of implied that Steve announced the 88K without directly saying he did
so. It may be just another rumor that they're treating as fact.

A little while ago (April 6), I saw this:

In article <27fcdce4.3a0@petunia.CalPoly.EDU> araftis@polyslo.CalPoly.EDU (Alex Raftis) writes:
>     And, at that, those are 15 or 20 *CISC* MIPS, which get a lot
>more work done than 15 or 20 RISC MIPS.  Further, you don't always
>have to up the clock speed to up the processor speed, as the upgrade
>from the 68030 to the 68040 exemplifies, so you don't have to end up
>with a processor that you could fry an egg on or one that has to use
>bulky, expensive SRAM for because the DRAMs available either don't
>run that fast or cost even more.

Since no one else has rebutted this, I will. This is all just plain wrong.
The issue of "CISC MIPS" versus "RISC MIPS" is a particular instance of
the widely held truth that MIPS == "Meaningless Instrumentation to
Propel Sales", that is, that MIPS is always so vague that it is meaningless.
Nonetheless, in particular cases one can run other, more meaningful benchmarks
to find out something closer to the truth.

And the truth is that the 68040 is *not* faster than the Sparc/88K/MIPS
processors. Your supposedly more powerful "CISC MIPS" are a phantom.

As for "having to up the clock speed to up the processor speed", this
is also without substance, because the improvement seen in going from
the 68030 to the 68040 was basically one of making the most commonly
executed and RISC-like instructions in the 68K operate at RISC-like
speeds. You can't get this improvement twice. Oh, sure, everyone will be
going for superscalar, where two instructions get executed every clock cycle,
but the RISCs will do this at least as effectively as CISCs (doubtless better,
in fact).

In other words, the playing field is more level now. The 68040 has improved
enough that it will benefit from increased clock speed *almost* as much
as RISCs do. And it will benefit from superscalar almost as much as
RISCs will. It was never the case that the 68K actually had some sort
of advantage there; you've got it backwards.

Don't forget, CISCs came first, and RISCs were introduced for very good
reasons. Find out what the reasons were/are before take shots in the dark.

And as for DRAM not being able to keep up with RISCs, that's even further
off the mark. DRAM speeds are as much an issue for CISC *performance* as
for RISCs; it is hardly an advantage to claim that because CISCs waste
cycles, that they therefore aren't limited by DRAM speeds. They certainly
are -- both CISCs and RISCs can either do useful work while waiting on
memory, or they cannot and must wait.

I have my own doubts about RISC as the ultimate in architecture, but they
are clearly the fastest way to do things in the *near-term*. The other
issues I'm interested in will probably not be competitive for another
5-10 years; we'll likely have to hit a performance plateau with superscalar
RISCs before it makes sense to start building in other directions.
	Doug
-- 
--
Doug Merritt		doug@eris.berkeley.edu (ucbvax!eris!doug)
		or	uunet.uu.net!crossck!dougm