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From: kenton@abyss.zk3.dec.com (Jeff Kenton OSG/UEG)
Newsgroups: comp.arch
Subject: Re: Bitfield instructions--a good idea?
Message-ID: <1991Apr17.142749.959@decvax.dec.com>
Date: 17 Apr 91 14:27:49 GMT
References: <1991Apr15.193425.3436@waikato.ac.nz> <712@seqp4.UUCP> <1991Apr17.174918.3458@waikato.ac.nz>
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Reply-To: kenton@abyss.zk3.dec.com (Jeff Kenton OSG/UEG)
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In article <1991Apr17.174918.3458@waikato.ac.nz>, ldo@waikato.ac.nz
(Lawrence D'Oliveiro, Waikato University) writes:
|> In article <712@seqp4.UUCP>, jdarcy@seqp4.ORG (Jeff d'Arcy) mentions
|> the bitfield instructions on the Motorola 88K processor family.
|> 
|> Someone else has kindly e-mailed me a description of the 88K bitfield
|> instructions. They are truly remarkable animals, except for some reason
|> the variable versions take *both* the offset and field width (as bitfields)
|> from the same register.
|> 
|> In other words, if you were dealing with a variable bitfield, you'd need
|> another sequence of bitfield instructions (using fixed, immediate values for
|> the width and offset) to set up the operands for the first one!
|> 
|> Why did they design the 88K instructions to pack two operands into
|> one register?
|> 

I don't remember any case where having them in the same register (you want
them in 2 registers?) was inefficient.  Furthermore, the instruction set
encoding has space for 3 register specifiers -- source, destination and
width/offset in this case.  There would be no way to encode width and offset
separately.

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==	jeff kenton		Consulting at kenton@decvax.dec.com        ==
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