Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!ucsd!ucbvax!mtxinu!taniwha!paul
From: paul@taniwha.UUCP (Paul Campbell)
Newsgroups: comp.arch
Subject: Re: Floating Point Risc
Message-ID: <826@taniwha.UUCP>
Date: 21 Apr 91 05:07:53 GMT
References: <1991Apr20.063947.12811@sbcs.sunysb.edu>
Reply-To: paul@taniwha.UUCP (Paul Campbell)
Organization: Taniwha Systems Design, Oakland
Lines: 24

In article <1991Apr20.063947.12811@sbcs.sunysb.edu> jallen@eeserv1.ic.sunysb.edu (Joseph Allen) writes:
>
>How's this for a risc processor:  No integer instructions at all.  Addresses
>would be floating point too, but automatically INTed when presented to the
>address lines (or maybe normalized floating point numbers themselves could be
>used as addresses...).  There would be one floating point number per integer
>address or 4 or 8 bytes per address (load byte at location 123.75).  When
>bytes are loaded/stored they're also converted to/from floating point while
>they're in the registers.  

Sounds like a B6700 et al. all numbers are FP, the FP representations are
chosen such that a number with a 0 exponent happens to be an integer with
the MSB bits == 0. (Of course they use sign/magnatude rather than 2's
complement so they can get away with it ...)


	Paul


-- 
Paul Campbell    UUCP: ..!mtxinu!taniwha!paul     AppleLink: CAMPBELL.P
There once was a landlord from Berkeley,Whose apartments were rundown and dirty
He decided to run,			For the rent-board, and won!
Now his tenants are homeless and hurting.