Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!think.com!spool.mu.edu!uwm.edu!bionet!agate!usenet.ins.cwru.edu!gatech!hubcap!mark From: mark@hubcap.clemson.edu (Mark Smotherman) Newsgroups: comp.arch Subject: Re: Sun4 caches? Message-ID: <1991Apr23.155611.29513@hubcap.clemson.edu> Date: 23 Apr 91 15:56:11 GMT Article-I.D.: hubcap.1991Apr23.155611.29513 References: Organization: Clemson University Lines: 29 From article , by prl@iis.ethz.ch (Peter Lamb): > I would appreciate it if someone could send me a short summary > of the cache structure for Sun4's (especially SparcStations). SPARCstation 1 (SS1): IU - LSI Logic L64801 FPU - Weitek WTL3170 clock - 20 MHz cache - combined I+D, 64Kb, virtually addressed with OS-managed alias avoidance, 16-byte lines, direct mapped, write through, no write allocate on write miss, no read through on read miss, 32-bit bus from memory to cache, 32-bit bus from cache to processor memory - 2-cycle load, 3-cycle store, 11-cycle cache refill buffer - 1-word write buffer in cache (double-word stores stall) (From: A.V. Bechtolsheim and E.H. Frank, "Sun's SPARCstation 1: A Workstation for the 1990s," IEEE Spring Compcon, San Francisco, Feb.-March 1990, pp. 184-188.) I believe that the information above also holds for the SS1+, with the exception that the clock rate is 25 MHz. Would someone from Sun please confirm the above and give a similar description for the SS2? Thanks. -- Mark Smotherman, CS Dept., Clemson University, Clemson, SC 29634-1906 mark@cs.clemson.edu or mark@hubcap.clemson.edu