Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!spool.mu.edu!uunet!mcsun!tuvie!mike
From: mike@vlsivie.tuwien.ac.at (Michael K. Gschwind)
Newsgroups: comp.arch
Subject: Re: Snakebytes (HP process technology)
Message-ID: <2413@tuvie.UUCP>
Date: 19 Apr 91 15:36:31 GMT
References: <40812@cup.portal.com> <32580016@hpcuhe.cup.hp.com> <00947104.8B2D8080@KING.ENG.UMD.EDU>
Sender: news@tuvie.UUCP
Organization: Vienna University of Technology
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In article <00947104.8B2D8080@KING.ENG.UMD.EDU> sysmgr@KING.ENG.UMD.EDU (Doug Mohney) writes:
>So the TI floating-point goodie is the most expensive chip sitting in your box,
>due to the fabrication process, among other things? (TI: Good, but pricy) Could
>you offer a Real Cheap Snake (snakette?) with a goal of 20MIPS/5K given the
>current technology? 
>
>> While Hitachi is not involved in the Series 700, they have licensed the 
>>PA-RISC architecture and are
>>expected to produce PA-RISC chips in the future.
>
>Will they be offering complementary low-end machines to the Snake? Have any
>other companies considered licensing PA-RISC? 

Samsung is supposed to build low-end Snakes. According to what I hear 
from HP, they will cut back on floating point performance to achieve
this goal. 

The HP people I talked with only mentioned Hitachi and Samsung as
licensees. 

					mike



Michael K. Gschwind, Dept. of VLSI-Design, Vienna University of Technology
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