Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!elroy.jpl.nasa.gov!decwrl!csus.edu!ucdavis!csusac!unify!longbow!ttank!fbits!Mariusz
From: Mariusz@fbits.ttank.com (Mariusz Stanczak)
Newsgroups: comp.sys.3b1
Subject: Re: Hardware freaks Unite (on this one)
Keywords: 3B1, cache, hardware project suggestion.
Message-ID: <101@fbits.ttank.com>
Date: 21 Apr 91 03:01:29 GMT
References: <1991Mar26.023948.3966@i88.isc.com> <6386@acorn.co.uk> <6464@acorn.co.uk>
Organization: Forth Bits
Lines: 27

In article <6464@acorn.co.uk>, agodwin@acorn.co.uk (Adrian Godwin) writes:
> They may assume things about the bus timing - the critical timings on one
[...]
> Control registers may - or may not - be similar.
[...]
> The higher 680x0 processors
> have a different interrupt/exception stack frame to the 68000, and the 
> system needs also to recognise memory that isn't in it's normal addressing 
> range. A different mechanism is used to load the PSR.
[...]
> -- 
> --------------------------------------------------------------------------
> Adrian Godwin                                        (agodwin@acorn.co.uk)

Thank you for your comments, Adrian.  For those reasons, especially
the stack frame differences... that affects everything(!) a drop-in uP
upgrade doesn't sound like a viable route to go, though I'd love to be
proven otherwise.  A cache would be a much less obtrusive way to boost
a little the, already adequate, performance of this machine, with full
compatibility assured.  ...it'd be cheaper too ;-) (well maybe not, 25ns
memory still isn't a commodity item, but SIMPLER it would be for sure!)

-Mariusz
-- 
INET: Mariusz@fbits.ttank.com
CIS : 71601.2430@compuserve.com
UUCP: ..!uunet!zardoz!ttank!fbits!Mariusz