Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!uwm.edu!psuvax1!news From: melling@cs.psu.edu (Michael D Mellinger) Newsgroups: comp.sys.amiga.advocacy Subject: Re: MIPS (was Re: NeXT Press Release) Message-ID: <&ubG#27w1@cs.psu.edu> Date: 23 Apr 91 01:07:12 GMT References: <4c9Go-jt1@cs.psu.edu> <47555@ut-emx.uucp> <8107@jhunix.HCF.JHU.EDU> Sender: news@cs.psu.edu (Usenet) Distribution: comp Organization: Penn State Computer Science Lines: 21 In-Reply-To: barrett@jhunix.HCF.JHU.EDU's message of 23 Apr 91 00:53:29 GMT Nntp-Posting-Host: sunws5.sys.cs.psu.edu In article <8107@jhunix.HCF.JHU.EDU> barrett@jhunix.HCF.JHU.EDU (Dan Barrett) writes: In article melling@cs.psu.edu (Michael D Mellinger) writes: >>The 1+ has a few MIPS on the 040. >WRONG. The Sparc 1+ is rated 15mips and so is the 68040. I was under the impression that RISC MIPS and CISC MIPS are not directly comparable like this. Actually, the best way to compare performance is with SPECmarks. CISC instructions in general do more than RISC instructions. Therefore a 15 mip CISC(the NeXT) is probably a little faster than a 15 mip RISC(Sparc 1+). Although, I did have an instructor that said the difference in the amount of work done by a CISC instructions in comparison to RISC instruction is overemphasized. To sum it it, look at the SPECmarks. Mips are lies. -Mike