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From: dwboyce@acsu.buffalo.edu (Doug Boyce)
Newsgroups: comp.sys.amiga.advocacy
Subject: Re: MIPS (was Re: NeXT Press Release)
Message-ID: <72561@eerie.acsu.Buffalo.EDU>
Date: 23 Apr 91 16:50:42 GMT
References: <47555@ut-emx.uucp> <hpdG+zeu1@cs.psu.edu> <8107@jhunix.HCF.JHU.EDU>
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In article <8107@jhunix.HCF.JHU.EDU> barrett@jhunix.HCF.JHU.EDU (Dan Barrett) writes:
>In article <hpdG+zeu1@cs.psu.edu> melling@cs.psu.edu (Michael D Mellinger) writes:
>>>The 1+ has a few MIPS on the 040.
>>WRONG.  The Sparc 1+ is rated 15mips and so is the 68040.
>
>	I was under the impression that RISC MIPS and CISC MIPS are not
>directly comparable like this.

Another thing is that the 68040 is blurring the line between CISC and RISC.
A RISC chip is supposedly one that executes one instruction per clock
cycle. The '040 averages 1.3 instructions per, making them more similar
than dissimilar (in this specific instance).

-- 
Doug Boyce    dwboyce@acsu.buffalo.edu

"Speedballs are interesting if you aren't the cannoneer doing the running."
"Where's that Lotto ticket, I want a NeXT NoW!"