Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!swrinde!elroy.jpl.nasa.gov!lll-winken!iggy.GW.Vitalink.COM!widener!dsinc!bagate!cbmvax!daveh From: daveh@cbmvax.commodore.com (Dave Haynie) Newsgroups: comp.sys.amiga.hardware Subject: Re: Amiga Custom Chips Message-ID: <20801@cbmvax.commodore.com> Date: 20 Apr 91 04:24:12 GMT References: <9104172234.AA04604@sun2.emr.ca> Reply-To: daveh@cbmvax.commodore.com (Dave Haynie) Organization: Commodore, West Chester, PA Lines: 35 In article <9104172234.AA04604@sun2.emr.ca> fillmore@SUN2.EMR.CA (Bob Fillmore) writes: >In article <20298@cbmvax.commodore.com> daveh@cbmvax.commodore.com (Dave Haynie) writes: >A question I have been meaning to ask for a while: >How hard would it be to implement phased memory banks in the Amiga, >a technique used by mainframe manufacturers to implement fast memory >by using slow DRAM chips? That's pretty common in microcomputers too, within reason. Most of the implementations I've seen keep the bank number to two, since in modern memories TRP < TRAS. The main problem is the increase in memory controller size. You typically need a set of data buffers, separate addresses, RAS*, and CAS* lines for each bank. What this technique does, for those unfamiliar with it, is hide the row precharge time for each bank of memory, most of the time, since you have a real good chance of alternating between banks for each memory access. You basically get DRAM that runs limited by access time rather than by cycle time. This can be significant -- for example, a 100ns DRAM typically have a 190ns cycle time. However, unless you can build the system to account for consecutive access to the same bank, you're in trouble, because its impossible to guarantee, at least in most systems, that the banks will always alternate. Most CPU systems can easily adjust dynamically to memory speed by inserting wait states. Amiga chips, on the other hand, can't -- they're exactly slaved to run certain memory cycles during certain "slots" in the video scan, and can't handle any memory wait at all. That's not to say some bank interleave scheme couldn't work. It is a perfectly valid way to generally speed up operation, though also a bit expensive in the pincount area for an already tight Amiga system chip. >Bob Fillmore, Systems Software & Communications email: fillmore@emr1.emr.ca -- Dave Haynie Commodore-Amiga (Amiga 3000) "The Crew That Never Rests" {uunet|pyramid|rutgers}!cbmvax!daveh PLINK: hazy BIX: hazy "That's me in the corner, that's me in the spotlight" -R.E.M.