Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!jarthur!nntp-server.caltech.edu!toddpw
From: toddpw@nntp-server.caltech.edu (Todd P. Whitesel)
Newsgroups: comp.sys.apple2
Subject: Re: ASIC Prototype
Message-ID: <1991Apr19.204954.5191@nntp-server.caltech.edu>
Date: 19 Apr 91 20:49:54 GMT
References: <51671@apple.Apple.COM> <1991Apr18.190155.5198@m.cs.uiuc.edu> <109618@tut.cis.ohio-state.edu> <1991Apr19.002759.28135@m.cs.uiuc.edu> <5582@ns-mx.uiowa.edu>
Distribution: usa
Organization: California Institute of Technology, Pasadena
Lines: 13

jmueller@umaxc.weeg.uiowa.edu (Jim Mueller) writes:

>I recall Bill Heineman stating he tried upgrading his zip chip by changing
>crystals, poswer supply, etc, and only get it up to 10 Mhz whereas with
>the TWGS he has it running at roughly 13Mhz. Apparently Zip knows something
>Bill does not. Personally, I favor the simpler design of the Zip. Wow, 20Mhz...
>If only they had a decent size cache now.

What's wrong with 64k? Caches above 64-128k generally don't justify their
extra cost.

Todd Whitesel
toddpw @ tybalt.caltech.edu