Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!ucsd!ucrmath!rhyde
From: rhyde@ucrmath.ucr.edu (randy hyde)
Newsgroups: comp.sys.apple2
Subject: Re: ASIC Prototype
Message-ID: <13725@ucrmath.ucr.edu>
Date: 21 Apr 91 03:06:59 GMT
References: <626@generic.UUCP>
Organization: University of California, Riverside
Lines: 7

I've been attempting to stay out of this argument, but I do have one
question and comment:  As I understand it, this single prototype chip
is running in a 2.8 Mhz GS.  Is this correct?  if so, testing it at
2.8 Mhz is somewhat useful, but that only proves that they've built a
2.8 Mhz chip, not a 17Mhz chip.  We need a 17mhz test bed to test a
17 Mhz chip.  My apologies if I've misunderstood the situation.
*** Randy Hyde