Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!ncar!midway!mimsy!haven!ncifcrf!lhc!adm!smoke!gwyn
From: gwyn@smoke.brl.mil (Doug Gwyn)
Newsgroups: comp.sys.apple2
Subject: Re: speed loss
Message-ID: <15909@smoke.brl.mil>
Date: 20 Apr 91 20:11:12 GMT
References: <9104181535.AA28525@apple.com>
Organization: U.S. Army Ballistic Research Laboratory, APG, MD.
Lines: 15

In article <9104181535.AA28525@apple.com> THROOP@GRIN1.BITNET ("Throop,Henry B") writes:
>Do other computers (Mac, IBM, for example) also suspend the CPU occasionally
>to refresh the DRAMs, or do they have a seperate coprocessor or something
>like that to do it?

There are all sorts of hardware implementation techniques.  Most "real"
computers don't let memory refresh interfere with ALU operation except
in very rare circumstances when an uncached memory location is needed
for an operation at at that very instant it is being refreshed.

>Does this have anything to do with why IBM systems use 9 RAM chips (for
>parity checking?) where 8 do in the gs?

No, the parity bit is for error detection; it has nothing to do with
memory refresh speed etc.