Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!ncar!midway!mimsy!haven!ncifcrf!lhc!adm!smoke!gwyn
From: gwyn@smoke.brl.mil (Doug Gwyn)
Newsgroups: comp.sys.apple2
Subject: Re: ASIC Prototype
Message-ID: <15912@smoke.brl.mil>
Date: 20 Apr 91 20:33:37 GMT
References: <1991Apr18.190155.5198@m.cs.uiuc.edu> <109618@tut.cis.ohio-state.edu> <1991Apr19.002759.28135@m.cs.uiuc.edu>
Organization: U.S. Army Ballistic Research Laboratory, APG, MD.
Lines: 15

In article <1991Apr19.002759.28135@m.cs.uiuc.edu> bazyar@cs.uiuc.edu (Jawaid Bazyar) writes:
>They took a Zip and and hopped it up to 14MHz (the whole power supply, etc
>shebang). Then they did all the same mods to a Transwarp and could only get
>11MHz out of it.  Meaning the Zip is a whole lot more robust (nothing I
>didn't already know).

The conclusion does not follow from the observations, even assuming it
was clear what you mean by "robust".  There are many factors in a given
digital circuit that can limit its maximum supportable clock rate; they
don't necessarily indicate anything wrong with the design.  My previous
estimate of an upper limit to TWGS 32K cache speed, based on its circuit
components, was 12MHz, give or take a little; 11MHz may be correct.

What we really need is to be able to use faster processor clock rates
with no alterations to normal Apple IIGS power supply operation.