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From: akcs.joehorn@hpcvbbs.UUCP (Joseph K. Horn)
Newsgroups: comp.sys.handhelds
Subject: Re: Request for timing info for Saturn processor
Message-ID: <2813b9a4:2736.2comp.sys.handhelds;1@hpcvbbs.UUCP>
Date: 23 Apr 91 04:40:04 GMT
References: <723@uqcspe.cs.uq.oz.au> <28072fae:2736.1comp.sys.handhelds;1@hpcvb
Lines: 43

Paul Dale (aka grue@cs.uq.oz.au, Frobozz, and Pauli) on Thu Apr 11 1991
wrote:

> I'm writing a small (??) program for the 48 and I would like to know
> some details about the timing of some of the instructions available
> (I don't have the tech doc for the Saturn processor).  I particular,
> I would like to know the timings of the following (using Alonzo's
> notation):
>
> 81A?0?  Move.? a/c, r?
> 81A?1?  Move.? r?, a/c
> 81A?2?  Swap.? a/c, r?
> 10?     Move.w a/c, r?
> 11?     Move.w r?, a/c
> 12?     Swap.w a/c, r?
> BF?     Srn.w reg       ? = [4,5,6,7]
> 81?     Rrn.w reg       ? = [4,5,6,7]
> [...]
> 13?     swap.a  a/c, d?
> 14?     move.a  ?, ?    indirect memory references
> 16?     add.a   ?+1, d0
> 18?     sub.a   ?+1, d0

Hope this isn't too late, Paul:

The 81A??? opcodes are "new" (not found in the HP 71) and therefore not
documented in the 71 IDS, which is the only Saturn timing info we have.

10?, 11?, 12? and BF? take 19 clock cycles.

Rrn.w reg takes 21 cycles.

13? Swap.a a/c,d? takes 8 cycles.
14? Move.a ?,? (indirect) takes 17 cycles.
16? Add.a ?,d? takes 7 cycles.
18? Sub.a ?,d? takes 7 cycles.

The accuracy of the above is not guaranteed, since the microcode for
these instructions may have changed since the HP 71.  The loose rule of
thumb I use is that an instruction takes as many clock cycles as the
number of digits in its opcode PLUS the number of digits of data that
are operated upon.

--  Joseph K. Horn  --  Peripheral Vision, Ltd.  --