Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!think.com!mintaka!ogicse!intelhf!ichips!ichips!glew From: glew@pdx007.intel.com (Andy Glew) Newsgroups: comp.sys.ibm.pc.hardware Subject: Re: Caching and VGA (was: Comparing 486 to 386 Systems) Message-ID: Date: 22 Apr 91 01:59:38 GMT Article-I.D.: pdx007.GLEW.91Apr21185938 References: <1991Apr6.045408.15395@agate.berkeley.edu> <1991Apr7.170017.23962@news.cs.indiana.edu> <1991Apr7.232941.21382@agate.berkeley.edu> <1991Apr8.154643.784@saturn.uucp> <1991Apr18.030753.6037@cc.helsinki.fi> Sender: news@omews63.intel.com (News Account) Organization: Intel Corp., Hillsboro, Oregon Lines: 43 In-Reply-To: osmoviita@cc.helsinki.fi's message of 18 Apr 91 03:07:53 GMT >>>Many 486 system allow one to disable caching of memory in the >>>upper address ranges. This is important for memory-mapped I/O cards >>>such as VGA, etc. >> >>How does VGA (SuperVGA) etc. suffer from caching? > >If you cache writes, then the cache grabs the write and the VGA card >doesn't get it. (1) the i486(tm) on-chip cache is write-through, so this scenario cannot happen within the on-chip cache. It could happen, however, in an i486(tm) system with an off-chip as well as the on-chip cache. (2) In general it is not a good thing to cache I/O memory locations. Many I/O memory locations are "active" - i.e. a read operation may have a side effect, like taking a character off a queue. Caching data so that subsequent reads do not go to the bus means that successive reads will return the same character - not at all what you want. It is possible to imagine caching some aspects of memory mapped I/O. For example, one might put a frame buffer in write through cached memory (but put all the control registers in uncached memory). Then, bitblts in the frame buffer might gain the advantage of caching for reads, but the writethrough would guarantee that all things drawn are seen immediately. Usually, however, the safe and conservative thing to do is not to cache any memory mapped I/O locations. What systems do cache I/O locations? What assumptions do they make (i.e. do they assume write-through? are there control registers read-safe?) How much performance benefit do they get? Please email replies to me, as I do not get to read this newsgroup as often as I should. -- Andy Glew, glew@ichips.intel.com Intel Corp., M/S JF1-19, 5200 NE Elam Young Parkway, Hillsboro, Oregon 97124-6497 This is a private posting; it does not indicate opinions or positions of Intel Corp.