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From: josephc@nntp-server.caltech.edu (Simplelogic (Joseph))
Newsgroups: comp.sys.misc,sci.engr
Subject: 74LS is too slow. Maybe?
Summary: Is 74LS series TTL Logic too slow nowadays?
Keywords: 74LS TTL Logic Computer Design Timing
Message-ID: <1991Apr23.013116.3769@nntp-server.caltech.edu>
Date: 23 Apr 91 01:31:16 GMT
Organization: California Institute of Technology, Pasadena
Lines: 43

Hello fellow netters.

I am currently putting together a NEC V-53 computer project.  Basically
speaking, a high-performance Intel 80186-like processor with what I hope
is zero-wait-state memory, all clocking at a nice and decent 16-MHz.

According to the documentation that I have, the V-53 requires a 80ns 
access time to memory.  That's not too bad of a problem if the CPU was
attached directly to the DRAM's (will be using -70ns SIMM's); however,
in order to implement direct-fly-by DMA (where the device puts the data
on the data bus while the memory writes it in, or vice-versa), I need to
buffer the output of the CPU, and the memory, and run them both through
the system bus (with expansion, of course).

My problem is that a couple of 74LS gates will already add up to about 40ns
to the access time...  Ergo, wait states - something that I don't want
to have if I can get away without it.

How have current 386 and 68040 (and other) based systems get around this
timing bottle-neck?  74F/74ALS series chips?  Unfortunately, there is a
very limited availability, both in terms of what's being manufactured, and
in terms of sourcing from distributors in small quanitities.

I'd like some input as to how I can speed up overall access time while 
maintaining a fully-buffered architecture (crucial because it will be on
a bus with lots of device on it).

Thanks.

-- Joseph

(P.S., if anyone is curious, I am building a telephone exchange using
   National Semiconductor's SLIM units which basically will take care of
   80% of the interfacing and analog <-> digital conversion on one 'chip'.
   The system is on a S-100 sized backplane, but with completely redefined
   lines, and [heavens!] -48V DC and two -48V "AC" lines...)



-- 
Joseph I. Chiu, Department of Computer Science, Calif. Inst. of Technology
1-57 Fleming House, Caltech, Pasadena 91126.   (818) 585-0393
josephc@coil.caltech.edu                     ...I don't know what I don't know