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From: jlodman@beowulf.ucsd.edu (Michael Lodman)
Newsgroups: comp.sys.ncr
Subject: Re: NCR's 3000 series to replace towers???
Message-ID: <18490@sdcc6.ucsd.edu>
Date: 20 Apr 91 23:11:51 GMT
References: <391@wybbs.mi.org> <697@ncrsea.Seattle.NCR.COM> <5907@holston.UUCP>
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Organization: CSE Department, UC San Diego
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In article <5907@holston.UUCP> barton@holston.UUCP (Barton A. Fisk) writes:
>What bus is NCR going to go with on the high end 486/50 systems?

In the level 7, it is my understanding that the processor-memory interface
will be a proprietary very wide (128 bit) bus. I/O will be handled through 
various optional attached buses, including MC and MBII. I don't know how many
processors NCR will be placing in a single cabinet of the
level 7, but my (somewhat educated) guess is 4-8. These separate cabinets
will be interconnected through a new verion of the Teradata Y-Net being 
specifically developed for this product and referred to as the BY-Net
(I think "B" stands for "Big", but I'm just guessing). Thus, the
thousands of processors referred to by NCR will be attached through the BY-Net.

>Proprietary buses tend to fly in the face of open systems in my
>opinion. 

Depending on what buses you are referring to, I agree. Unfortunately, there
isn't a standard bus available which supports the transfer bandwidth
between processors and memory which NCR needs to sustain in the level 7.
The I/O buses will be completely industry standard, except that NCR may choose
to support some of their older proprietary I/O standards as well to
bring customers over to the new system.

>Maybe someone could comment on whether the MC bus will handle
>multiple processors? Or is NCR thinking about EISA? I read a  
>comment by an NCR marketing spokesman in PW where he stated that
>one of the targets was the Systempro.

The MC bus will handle multiple processors. I really doubt that anyone would 
want to hang memory off it as well, though. I don't think NCR has EISA
plans, but my information could well be dated. I would appreciate any
corrections if I am incorrect in my understanding of the level 7.


-- 
Michael Lodman	Department of Computer Science Engineering
	University of California, San Diego
jlodman@cs.ucsd.edu			(619) 672-1673