Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!usc!jarthur!nntp-server.caltech.edu!fjs From: fjs@nntp-server.caltech.edu (Fernando J. Selman) Newsgroups: comp.sys.next Subject: Re: RISC vs. CISC -- SPECmarks Keywords: MIPS are MEANINGLESS Message-ID: <1991Apr20.060649.6168@nntp-server.caltech.edu> Date: 20 Apr 91 06:06:49 GMT References: <8lbG1vdl1@cs.psu.edu> <1991Apr18.180538.1@sif.claremont.edu> <339@nic.cerf.net> Organization: California Institute of Technology, Pasadena Lines: 14 Just my 2 cents contribution to this discussion. When comparing the Next to Sparc1+ and 2 I found that for applications that are not cache intensive the Next is equivalent to the Sparc 1+ (and by extension 1/2 the speed of the Sparc 2). When doing a cache intensive application (25000 body simulation) the relative efficiency of the Sparc 1+ double with respect to the Next. I conclude from this that at least this RISC chip is not more efficient than the 68040, the difference being attributed to the cache. The NextWorld bechmarks seem to have been done in the regime when the cache is not important, this seem to be the reason why the Sparc 2 looks there only twice as fast as the Next. Fernando