Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!jarthur!sif.claremont.edu!greg
From: greg@sif.claremont.edu (Tigger)
Newsgroups: comp.sys.next
Subject: Re: RISC vs. CISC -- SPECmarks
Message-ID: <1991Apr22.165148.1@sif.claremont.edu>
Date: 22 Apr 91 23:51:48 GMT
References: <9104220802.AA09560@LL.MIT.EDU>
Sender: news@jarthur.Claremont.EDU
Organization: Pomona College
Lines: 13

In article <9104220802.AA09560@LL.MIT.EDU>, preston@LL.MIT.EDU (Steven Preston) writes:
> 
> Yes, it is clear that RISC has become a misnomer; it (RISC) now means that
> the average cycles per instruction is about 1 or less.

RISC has been a misnomer since before it came out of the labs.  I don't know
about the early IBM prototypes, but I'm pretty sure that every single 
commercially produced RISC design has had a larger instruction set than the
6502 in my old Apple II.  Does that make my old Apple II an early RISC
workstation?  I somehow don't think so...

|   Greg Orman                                        Let's get lost       |
|   greg@pomona.claremont.edu                            - Fieger/Averre   |