Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!wuarchive!udel!rochester!pt.cs.cmu.edu!zardoz.club.cc.cmu.edu!ddj From: ddj@zardoz.club.cc.cmu.edu (Doug DeJulio) Newsgroups: comp.sys.next Subject: Re: RISC vs. CISC -- SPECmarks Message-ID: <12753@pt.cs.cmu.edu> Date: 23 Apr 91 04:10:34 GMT References: <9104220802.AA09560@LL.MIT.EDU> <1991Apr22.165148.1@sif.claremont.edu> Organization: Castle Anthrax, Pittsburgh Lines: 17 In article <1991Apr22.165148.1@sif.claremont.edu> greg@sif.claremont.edu (Tigger) writes: >RISC has been a misnomer since before it came out of the labs. I don't know >about the early IBM prototypes, but I'm pretty sure that every single >commercially produced RISC design has had a larger instruction set than the >6502 in my old Apple II. Does that make my old Apple II an early RISC >workstation? I somehow don't think so... Naw. It's Reduced instruction set, not Tiny instruction set (TISC?). Way back then, small instruction sets were normal, so there wasn't much to reduce. Only after the popularity of chips with huge clunky instruction sets (cf. vax "polysolve" instruction) and bizzarre architectures (cf. 8086) could "RISC" become an apropriate term... -- DdJ Disclaimer: I *like* the VAX, *and* the 8086. I'd like 'em more if they weren't wierd-endian.