Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!apple!baum@apple.com
From: baum@apple.com (Allen Baum)
Newsgroups: comp.arch
Subject: Re: RISC Compare & Swap
Message-ID: <51947@apple.Apple.COM>
Date: 24 Apr 91 17:35:21 GMT
Sender: nntp@Apple.COM
Organization: Apple Computer
Lines: 25

I'm a bit confused about the explanation for Load Linked & Store Conditionally.
Supposedly, a compare&swap can be implemented with:

Ld_Linked old->tmp & set status
Branch if tmp!=match to .skip ;(didn't match)
Store_Conditionally new->old & clr status

Now, if some other processor jumps in between the Branch & store with
the whole sequence,does the status bit get cleared in this processor?
- if its a CAS sequence to the same lock, then it must, else both will
  think they got the lock
- if its a CAS sequence to a different lock, then you don't want to?
  (because you'll be reduced to spinning on that location) If not, how do
  you keep track of which location this processor is CAS'ing 
  (excuse the verbing of CAS, please). If you, say, have a reg. that keeps
  track of it, what happens if another process on the same processor gets
  swapped in & wants to CAS to anothe location- does it clobber the old
  address? etc. etc. etc....

It might be simply that ANY other Ld_Linked clears the status, so you spin
once (perhaps) & either fail if someone else grabbed it, or succeed if
someone else grabbed another lock. On the other hand, this isn't that
different than a test&set spinlock to a single global system-wide lock.

So..... what am I missing?