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From: vhs@britesun.radig.de (Volker Herminghaus-Shirai)
Newsgroups: comp.arch
Subject: Re: H1 details?
Message-ID: <1991Apr25.185728.1306@britesun.radig.de>
Date: 25 Apr 91 18:57:28 GMT
Organization: private site
Lines: 17

Andrea Gozzi writes:
>Anyone can write about how the H1 (T9000) from INMOS is supposed to
>run 150MIPS and 20MFLOPS? Architecture, clock, etc?
>What's the degree of compatibility with T800?
>Price?

A report in Markt&Technik magazine states that they have a 7 staged pipeline.
The second stage acts as an instruction sorter (thus doing what could actually
be done better by the compiler), rearranging instructions for parallel execution.
It also states that they can execute a maximum of eight instructions at once
in theis seven-staged pipeline (maybe including floating-point) and that more
than half of the chips transistors is used up by their seperate 16KB I/D-cache(s).

I do not remember any more details.



-- 
Volker Herminghaus-Shirai (vhs@britesun.radig.de)
panic: 80x86! Trying to vomit...