Newsgroups: comp.arch Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sdd.hp.com!news.cs.indiana.edu!ux1.cso.uiuc.edu!shair From: shair@ux1.cso.uiuc.edu (Bob Shair) Subject: Re: RISC vs. CISC -- SPECmarks Message-ID: <1991Apr27.162202.18043@ux1.cso.uiuc.edu> Organization: University of Illinois at Urbana References: <1991Apr22.044553.16805@mp.cs.niu.edu> <1991Apr26.073829.4625@kithrup.COM> Date: Sat, 27 Apr 1991 16:22:02 GMT Lines: 24 peter@ficc.ferranti.com (peter da silva) writes: >In article <1991Apr26.073829.4625@kithrup.COM>, sef@kithrup.COM (Sean Eric Fagan) writes: >> Or don't you realize you can only access one memory location at a time? >> (Well, not completely true, but true enough.) >Ah, the old Von Neumann botleneck. Time to apply RISC design techniques to >memory subsystems. How about multiported memory, or even banked memory? >Multiple data and address busses? Who knows, but memory subsystems are the >current bottleneck and something's gotta give. >-- >Peter da Silva. `-_-' peter@ferranti.com The IBM RISC 6000 (models 530 and above) has two-way memory interleaving, allowing two 64-bit words to be loaded or stored concurrently (but only to adjacent locations, I belive). Is this a first step in this direction? -- Bob Shair shair@chgvmic1.iinus1.ibm.com Scientific Computing Specialist SHAIR@UIUCVMD (bitnet) IBM Champaign