Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!usc!rutgers!njin!uupsi!ficc!peter From: peter@ficc.ferranti.com (peter da silva) Newsgroups: comp.arch Subject: Re: RISC vs. CISC -- SPECmarks Message-ID: Date: 27 Apr 91 16:09:08 GMT References: <1991Apr22.044553.16805@mp.cs.niu.edu> <11412@mentor.cc.purdue.edu> Organization: Ferranti International Controls Corporation Lines: 19 In article <11412@mentor.cc.purdue.edu>, hrubin@pop.stat.purdue.edu (Herman Rubin) writes: > In article , peter@ficc.ferranti.com (peter da silva) writes: > > Ah, the old Von Neumann botleneck. Time to apply RISC design techniques to > > memory subsystems. How about multiported memory, or even banked memory? > > Multiple data and address busses? Who knows, but memory subsystems are the > > current bottleneck and something's gotta give. > The CYBER 205/ETA 10 is a vector pipeline machine, with the most versatile > vector architecture I know of. Fine, but how does it pull those vectors into the CPU? The CPU can have a zillion registers a zillion words long, but it still has to read them from memory. So it does a lot of work in its vector units per instruction. But how quickly can it fill them? I'm envisioning a system where main memory is multi-way interleaved, where the CPU can read arbitrary words from each memory bank in a given cycle. -- Peter da Silva. `-_-' peter@ferranti.com +1 713 274 5180. 'U` "Have you hugged your wolf today?"