Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!uunet!zaphod.mps.ohio-state.edu!mips!mash From: mash@mips.com (John Mashey) Newsgroups: comp.arch Subject: Re: RISC vs. CISC -- SPECmarks Message-ID: <2744@spim.mips.COM> Date: 28 Apr 91 01:38:03 GMT References: <1991Apr24.170804.25670@kithrup.COM> <1991Apr25.025800.4377@mp.cs.niu.edu> <1991Apr26.073829.4625@kithrup.COM> Sender: news@mips.COM Organization: MIPS Computer Systems, Inc. Lines: 43 Nntp-Posting-Host: winchester.mips.com In article <1991Apr26.073829.4625@kithrup.COM> sef@kithrup.COM (Sean Eric Fagan) writes: >In article <1991Apr25.025800.4377@mp.cs.niu.edu> bennett@mp.cs.niu.edu (Scott Bennett) writes: (I either missed this, or it hasn't ogtten here yet.) >>Since a superscalar RISC can only be that way by pipelining, >>let's at least compare only pipelined architectures. FWIW, the MC68040 >>supposedly averages about 1.3 clock cycles per instruction because of >>the pipelining used. That obviously doesn't reach "superscalar", but >>it isn't terribly far off, either. > >Bullshit. It is *very* far off. Note the word "supposedly" in your >statement. Please look at John Mashey's figures; I think they indicate >slightly higher (1.4 or 1.5 CPI?) for the '40; on the other hand, the R3000 >got what, 1.2 or 1.3. > >> In any case, what really matters is how much work gets done per >>clock cycle, not how many instructions get done per cycle. > >No, it doesn't. What matters is *how quickly you can get your job done*. I >don't care if you can do a POLY instruction in 3 cycles; if you still take 2 >cycles to do an add, most current RISC chips will blow you away (unless your >application consists of POLY instructions). I'm sure the net doesn't want to again hear of the reasons why CPI is really only known by CPU architects. I'll repeat the observation, that at 25MHz, the best CISC micros get about 12-13 on SPECinteger, and either somewhat less on FP (68040), or a bunch less (i486), with 128KB external caches. At the same clock rate, the more efficient RISCs get 19-21 on integer, and either close to that, or higher on FP. (R3000, RS/6000, HP PA, etc.) (Many caveats here that I don't have time to type, about different configurations, who's running clocks at which rate, costs, etc, etc, etc.) Put another way, since the numbers in above post must refer to integer, CISCs need about 2 MHz/SPECint, efficient RISCs about 1.25. If you take MHZ/SPECint as a measureable approximation to cycles per EQUIVALENT instruction (as opposed to cycles/native instruction, which is fairly useless as a between-architecture metric by itself) you at least get a comparison that makes sense to argue about. -- -john mashey DISCLAIMER: UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems MS 1/05, 930 E. Arques, Sunnyvale, CA 94088-3650