Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sdd.hp.com!hplabs!hpfcso!maf
From: maf@hpfcso.FC.HP.COM (Mark Forsyth)
Newsgroups: comp.arch
Subject: Re: Snakes... HP process technology
Message-ID: <8840032@hpfcso.FC.HP.COM>
Date: 26 Apr 91 15:53:19 GMT
References: <1991Apr23.171051@agni.Berkeley.EDU>
Organization: Hewlett-Packard, Fort Collins, CO, USA
Lines: 13

>From: mehra@agni.Berkeley.EDU (Vivek Mehra)
>
>Does the new HP workstation use 3.3 volt in any portion of the
>CPU/FPU/caches/memory controller design?
>
>-vivek

The final stage of the output driver circuits for inter-chip I/O use a
3.3 volt supply to increase speed and reduce power and noise. All other
circuits (including the cache SRAMs) use 5.0 volts.

- Mark Forsyth
(standard disclaimer)