Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!apple!agate!ucbvax!ucdavis!csusac!unify!longbow!ttank!fbits!Mariusz
From: Mariusz@fbits.ttank.com (Mariusz Stanczak)
Newsgroups: comp.sys.3b1
Subject: Re: Hardware freaks Unite (on this one)
Summary: all in the numbers
Keywords: 3B1, cache, hardware project suggestion.
Message-ID: <104@fbits.ttank.com>
Date: 28 Apr 91 18:18:23 GMT
References: <1991Mar26.023948.3966@i88.isc.com> <6386@acorn.co.uk> <51582@rphroy.UUCP>
Organization: Forth Bits
Lines: 29

In article <51582@rphroy.UUCP>, tkacik@hobbes.cs.gmr.com (Tom Tkacik CS/50) writes:
> The 3B1 uses a 68010 processor running at 10MHz.  The rest of the system
[...]
> Memory speed is not the bottleneck.  The processor is the bottleneck.
[...]
> The 68010 uses 4 clock cycles to access one word of memory.
> At 10MHz, that's 400ns.  The memory used in the 3B1 is 150ns.  With all of
> the delays on the motherboard, (and through the 68010 itself), that work's
> out about right.  When slower memory is used, (like the ROM for example),
[...]
> Higher performance in the 3b1 will only be gained by either
> increasing the processor speed,
> or by putting in a more powerful processor (68020 or 68030).
[...]
> The problem with putting in a 68020 or 68030 has been hashed out before,
> (the interrupt stack frame problem, which required kernel hacks to get it
> to work).

Good stuff... the right numbers tell (to the right person) the story.
And, that just about closes the topic... doesn't it? (at least for me...
I better leave speedup ideas to the better equipped).  Still it'd be
nice (dream on boy ;-)).  And the one I still have (a "realizable fantasy")
is a SCSI I/F.  How is that progressing?

-Mariusz
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