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From: drtiller@uokmax.ecn.uoknor.edu (Donald Richard Tillery Jr)
Newsgroups: comp.sys.amiga.advocacy
Subject: Re: MIPS (was Re: NeXT Press Release)
Message-ID: <1991Apr24.043828.7213@uokmax.ecn.uoknor.edu>
Date: 24 Apr 91 04:38:28 GMT
References: <hpdG+zeu1@cs.psu.edu> <8107@jhunix.HCF.JHU.EDU> <72561@eerie.acsu.Buffalo.EDU>
Distribution: comp
Organization: Engineering Computer Network, University of Oklahoma, Norman, OK
Lines: 37

In a message From: dwboyce@acsu.buffalo.edu (Doug Boyce)

>In article <8107@jhunix.HCF.JHU.EDU> barrett@jhunix.HCF.JHU.EDU (Dan Barrett) writes:
>>In article <hpdG+zeu1@cs.psu.edu> melling@cs.psu.edu (Michael D Mellinger) writes:
>>>>The 1+ has a few MIPS on the 040.
>>>WRONG.  The Sparc 1+ is rated 15mips and so is the 68040.
>>
>>	I was under the impression that RISC MIPS and CISC MIPS are not
>>directly comparable like this.
>
>Another thing is that the 68040 is blurring the line between CISC and RISC.
>A RISC chip is supposedly one that executes one instruction per clock
>cycle. The '040 averages 1.3 instructions per, making them more similar
>than dissimilar (in this specific instance).
>

According to Motorola's Technical Data sheet on the MC68040:

"o 20 MIP Integer Performance
 o 3.5 MFLOP Floating-Point Performance
 o IEEE 754-Compatible FPU
 o Independent Instruction and Data MMUs
 o 4K-Byte Physical Instruction Cache and 4K-Byte Physical Data Cache
   Accessed Simultaneously
 o 32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous
   Interface
 o User-Object-Code Compatibility with All Earlier M68000 Microprocessors
 o Multimaster/Multiprocessor Support via Bus Snooping
 o Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper
   Maximize Throughput
 o 4-Gbyte Direct Addressing Range
 o Software Support Including Optimizing C Compiler and UNIX(R) System V Port"

Looks like this CISC chip is right in there with all those RISC chips and
you don't have to make any allowances like re-writing your code :-)

Rick Tillery