Path: utzoo!utgpu!news-server.csri.toronto.edu!eecg.toronto.edu!leblanc Newsgroups: comp.sys.amiga.advocacy From: leblanc@eecg.toronto.edu (Marcel LeBlanc) Subject: Re: MIPS (was Re: NeXT Press Release) Message-ID: <1991Apr24.213006.15124@jarvis.csri.toronto.edu> Organization: University of Toronto X-NewsReferences: <72561@eerie.acsu.Buffalo.EDU> <1991Apr24.043828.7213@uokmax.ecn.uoknor.edu> <1991Apr24.135141.21417@convex.com> Date: 25 Apr 91 01:30:06 GMT Lines: 30 swarren@convex.com (Steve Warren) writes: >I saw the SPECmarks numbers. What conclusion are you drawing from them? >It looked to me like the 68040 beat the SPARC more than the SPARC beat the >68040. But for the most part they were roughly comparable. In fact, their >performance was amazingly similar, considering the disparity in architecture >of the two CPUs. This is right in line with the statement above, that >"...this CISC chip is right in there with all those RISC chips..." The statement would be true if it read as "...this CISC chip [the 68040] is right in there with that one RISC chip [SPARC]..." ^^^^^^^^ The simple fact is that the SPARC-1 implementations are providing the WORST performance of any RISC processors, largely due to the shared instruction+data cache (bus, really). Also add to the fact that the 68040 has been available for all of 4 months now, while 25 MHz SPARCs have been available for 2.5 years! Today, SPARCs and R3000As are available in 40 MHz speeds, with newer implementations such as the 3-chip HP PA available at up to 66 MHz. For a 4 month old chip, the 68040 is not farring very well at all with "all those RISC chips...". >--Steve ._||__ DISCLAIMER: All opinions are my own. > Warren v\ *| ---------------------------------------------- Marcel A. LeBlanc -- Electrical Eng. Computer Group, Univ. of Toronto ----------------------------------------------------------------------- leblanc@eecg.toronto.edu else: uunet!utcsri!eecg!leblanc