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From: toddpw@nntp-server.caltech.edu (Todd P. Whitesel)
Newsgroups: comp.sys.apple2
Subject: Re: speed loss
Message-ID: <1991Apr24.200233.3702@nntp-server.caltech.edu>
Date: 24 Apr 91 20:02:33 GMT
References: <9104181535.AA28525@apple.com> <1991Apr20.080839.27678@ux1.cso.uiuc.edu> <1991Apr23.170359.19679@nevada.edu> <13842@ucrmath.ucr.edu>
Organization: California Institute of Technology, Pasadena
Lines: 20

rhyde@musial.ucr.edu (randy hyde) writes:

>A 17 Mhz 65816 requires outrageously fast RAM.  To get the invisible
>refresh it would need twice as outrageously fast RAM (something like
>5ns).  Since no one can afford a large stockpile of this stuff, I feel
>the *small* percentage of overhead required for refresh is reasonable. 
>BTW, as processors get faster, the percentage of overhead associated
>with refresh goes down (of course, memory has to get faster too...).

Come on, Randy, nobody's going to try to run a high speed 65816 directly
off of DRAMs. Cache SRAMs only need to be about 20-25 ns and those are
far more reasonable. A Zip GSX at 10 mhz with a WDC part only needs 55 ns
SRAMs, and the cache hit detect takes 10 ns, so a 20 mhz chip should be
able to get by with 20 (maybe 25) ns cache RAM. I can order those from
Newark -- my roommate chucked our last year's catalog so I don't have any
prices to quote right now. Last I remember 16K was about $20 so now a good
sized cache could probably be had for a few hundred.

Todd Whitesel
toddpw @ tybalt.caltech.edu