Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!sol.ctr.columbia.edu!trantor.harris-atd.com!charybdis!sonny
From: sonny@charybdis.harris-atd.com (Bob Davis)
Newsgroups: comp.sys.ibm.pc.hardware
Subject: I/O Bus and RAM Wait States Questions.
Message-ID: <6155@trantor.harris-atd.com>
Date: 28 Apr 91 01:53:44 GMT
Sender: news@trantor.harris-atd.com
Reply-To: sonny@trantor.harris-atd.com (Bob Davis)
Organization: Advanced Technology Dept., Harris ESS, Melbourne, FL
Lines: 21


	A 12mHz motherboard I have has a jumper which selects either
6 I/O wait states or 4 - depending on the jumper's position. Does the I/O
bus clock come from the 80286 cpu's 12 Mhz clock with simply enough
wait states (whatever *they* are) inserted to slow the effective bus clock
down to something around 8 mHz?
	Or is the I/O bus clock a divide-down from the 24 mHz oscillator
on the motherboard? And are the 6 or 4 wait states inserted to *further*
slow this divided clock?
	How long does a wait state last? What is the formula for
calculating effective clock or access rate given raw clock rate and
number of wait states both for I/O bus and for RAM memory?

	Thanks

_____________________________________________________________________________
Bob Davis, UofALA alum \\ INTERNET: sonny@trantor.harris-atd.com  |  _   _  |
Harris Corporation, ESS \\    UUCP: ...!uunet!x102a!trantor!sonny |_| |_| | |
Advanced Technology Dept.\\ AETHER: K4VNO          |==============|_/\/\/\|_|
PO Box 37, MS 3A/1912     \\ VOICE: (407) 727-5886 | I SPEAK ONLY | |_| |_| |
Melbourne, FL 32902        \\  FAX: (407) 729-3363 | FOR MYSELF.  |_________|