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From: byron@cc.gatech.edu (Byron A Jeff)
Newsgroups: comp.sys.m68k
Subject: Re: 68000 vs. 68020
Message-ID: <27292@hydra.gatech.EDU>
Date: 25 Apr 91 14:46:00 GMT
References: <12964@pasteur.Berkeley.EDU> <27178@hydra.gatech.EDU> <13017@pasteur.Berkeley.EDU>
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Organization: Georgia Institute of Technology
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In article <13017@pasteur.Berkeley.EDU> spp@zabriskie.berkeley.edu.UUCP (Steve Pope) writes:
>In article <27178@hydra.gatech.EDU> byron@cc.gatech.edu (Byron A Jeff) writes:
>#>In article <12964@pasteur.Berkeley.EDU> spp@zabriskie.berkeley.edu.UUCP (Steve Pope) writes:
>#>>
>#> [ Steve writes of a 68000 being easier to interface than a 68020.
>#>   I responded that '020 are easier to work with because of dynamic
>#>   bus sizing. ]
>
>I'm surprised to hear that the dynamic bus sizing applies to
>instruction fetches.  Motorola's documentation, so far as I
>can tell, specifically talks about dynamic sizing for operand
>transfers only (for the 68020).  If the dynamic sizing
>also applies to fetches then I agree with the above response.
>
>steve

Any device can specify its bus width (8,16, or 32 bits) for each and
any fetch, instruction fetches included.

Ask your local Motorola representative for the Application Note 
"A Minimum Configuration 68020 System". It contains a 68020 system
that only has 8 bit ports for everything (EPROM, RAM, and IO). 

BAJ
---
Another random extraction from the mental bit stream of...
Byron A. Jeff - PhD student operating in parallel!
Georgia Tech, Atlanta GA 30332   Internet: byron@cc.gatech.edu