Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!oakhill!marvin
From: marvin@oakhill.sps.mot.com (Marvin Denman)
Newsgroups: comp.sys.m88k
Subject: Re: Is the FPSR interlocked with the FPU pipe?
Message-ID: <1991Apr25.203450.20731@oakhill.sps.mot.com>
Date: 25 Apr 91 20:34:50 GMT
References: <1991Apr24.200412.7483@eagle.lerc.nasa.gov>
Reply-To: marvin@bushwood.UUCP (Marvin Denman)
Distribution: na
Organization: Motorola Inc., Austin, Texas
Lines: 31

In article <1991Apr24.200412.7483@eagle.lerc.nasa.gov> fsset@bach.lerc.nasa.gov (Scott E. Townsend) writes:
>This sounds too strange to be true, but is it possible for the FPSR to
>return 'too fresh' data?  Or put another way, why should the following two
>code fragments behave differently?
>
>#1
>	fdiv.ddd r8,r2,r4
>	fldcr	 r12,fcr62	; fcr62 == FPSR
>	bb1	 0,r12,@L21	; AFINX bit
>
>#2
>        fdiv.ddd r8,r2,r4
>	tb1	 0,r0,0		; trap not taken, but system 'synced'
>        fldcr    r12,fcr62
>        bb1      0,r12,@L21
>

On the 88100 there is no builtin interlock between floating point instructions
and reads or writes to the FPSR.  The "safe" way of modifying the FPSR is
to sync the processor just as your example did.  Future implementations of
the 88000 architecture may or may not need this synchronization, but it should
never cause you any problems other than an additional instruction.  Note that
if this was an fstcr to the FPSR, your value might be overwritten when the
fdiv completes.   I looked briefly through the 88100 User's Manual and I could
not find this behavior documented either, but I will continue to look.  


-- 
Marvin Denman
Motorola 88000 Design
cs.utexas.edu!oakhill!marvin