Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!mips!spool.mu.edu!uunet!kithrup!sef
From: sef@kithrup.COM (Sean Eric Fagan)
Newsgroups: comp.sys.next
Subject: Re: RISC vs. CISC -- SPECmarks
Message-ID: <1991Apr24.170804.25670@kithrup.COM>
Date: 24 Apr 91 17:08:04 GMT
References: <1991Apr10.155032.14786@data.com> <1991Apr15.165540.14270@agate.berkeley.edu> <1991Apr22.044553.16805@mp.cs.niu.edu>
Organization: Kithrup Enterprises, Ltd.
Lines: 15

In article <1991Apr22.044553.16805@mp.cs.niu.edu> bennett@mp.cs.niu.edu (Scott Bennett) writes:
>     Case in point.  By executing multiple complex instructions per cycle,
>the CISC would appear to benefit at least as much as the RISC, not as you
>state.

Nope, not really. That's the problem:  with a "CISC" instruction set, it's
really very difficult to go superscalar, at least compared to some "RISC"
instruction sets.  Why?  Because not enough registers, too many memory
references in a single instruction, or other small, niggling details.

-- 
Sean Eric Fagan  | "I made the universe, but please don't blame me for it;
sef@kithrup.COM  |  I had a bellyache at the time."
-----------------+           -- The Turtle (Stephen King, _It_)
Any opinions expressed are my own, and generally unpopular with others.