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From: wayner@CS.Cornell.EDU (Peter Wayner)
Newsgroups: comp.sys.next
Subject: Re: RISC vs. CISC -- SPECmarks
Message-ID: <1991Apr24.181932.17810@cs.cornell.edu>
Date: 24 Apr 91 18:19:32 GMT
References: <1991Apr10.155032.14786@data.com> <1991Apr15.165540.14270@agate.berkeley.edu> <1991Apr22.044553.16805@mp.cs.niu.edu> <1991Apr24.170804.25670@kithrup.COM>
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sef@kithrup.COM (Sean Eric Fagan) writes:

>Nope, not really. That's the problem:  with a "CISC" instruction set, it's
>really very difficult to go superscalar, at least compared to some "RISC"
>instruction sets.   Why?  Because not enough registers, too many memory
>references in a single instruction, or other small, niggling details.

In another sense, going "superscalar" is much easier with CISC
machines.  I think the Intel 486 does a PUSH instruction in one cycle.
In RISC land, this is a decrement and a load. The CISC designer just
needs to use enough silicon to pipeline the important instructions.
There is no need for complex logic to handle all the possible cases of
two instructions coming down the pipe. The RISC designer needs to
worry about generality.

This is just an academic nit, though, because I generally agree with 
you.



>-- 
>Sean Eric Fagan  | "I made the universe, but please don't blame me for it;
>sef@kithrup.COM  |  I had a bellyache at the time."
>-----------------+           -- The Turtle (Stephen King, _It_)
>Any opinions expressed are my own, and generally unpopular with others.
-- 
Peter Wayner   Department of Computer Science Cornell Univ. Ithaca, NY 14850
EMail:wayner@cs.cornell.edu    Office: 607-255-9202 or 255-1008
Home: 116 Oak Ave, Ithaca, NY 14850  Phone: 607-277-6678