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From: cmaeda@a.gp.cs.cmu.edu (Christopher Maeda)
Newsgroups: comp.sys.next
Subject: CISC vs. RISC, some real datapoints
Message-ID: <12787@pt.cs.cmu.edu>
Date: 25 Apr 91 05:05:20 GMT
Organization: Carnegie-Mellon University, CS/RI
Lines: 39

I went to a talk on the 68040 last week.  Neat chip.
Performance-wise, there isn't much difference between 
the supposedly-CISC 68040 and a RISC chip.  The 040
has a pipeline depth of 6 or 7 clocks (I can't remember
the slide exactly) while the MIPS chip has a depth of 5,
at least according to Hennesey&Patterson's book which was
based on the R2000 and R3000.  Both chips get 1 clock per
instruction on straight line code.  The 040 takes 2 clocks
for taken branches.  I forget what the MIPS chip takes.

So the only differences I can see between an 040 and an R3000
are the pipeline depth, the amount of cache, and the number
of registers.  The R3000 is superior in all three of these
categories (it has oodles of registers and uses off-the-shelf
SRAM's for cache) which explains the slightly better performance.
They both have similar (ie memory<->register) instruction sets
so the CISC mips vs RISC mips is a non-argument.  On the other hand,
a PC based on the R3000 is likely to be out of most people's
reach for at least another year.

It took Moto 3 years to design and build the thing.  The guy giving
the talk said it's taken them about 3 years for each chip in the
68k family.  (68050 in 1993?)  Their cad tools have been keeping pace
with the increased complexity.  They used a fast prototype approach to
debug the chip since they didn't have enough time to do simulations of
the full chip (1.2 million transistors).  To make up for it, they used
a scanning electron microscope to find bugs and (get this) a focused
ion beam to fix them.  They also put sets of spare gates in various
places on the chip so they could splice them in with the ion beam
when they needed to.  Who says you can't have jumper wires in
silicon?



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