Path: utzoo!utgpu!news-server.csri.toronto.edu!rpi!zaphod.mps.ohio-state.edu!samsung!olivea!uunet!kithrup!sef From: sef@kithrup.COM (Sean Eric Fagan) Newsgroups: comp.sys.next Subject: Re: RISC vs. CISC -- SPECmarks Message-ID: <1991Apr26.163303.8614@kithrup.COM> Date: 26 Apr 91 16:33:03 GMT References: <1991Apr18.180538.1@sif.claremont.edu> Organization: Kithrup Enterprises, Ltd. Lines: 21 In article scott@texnext.gac.edu (Scott Hess) writes: >If you look, you'll see that all of the chips that have been created in the >past couple years seem to be RISC chips (this was brought to my attention >by a prof in one of my classes just this spring). It seems to be true! >What it makes one wonder is whether the naming of chips like the RIOS >RISC is done because they are really RISC, or because RISC is what >people want. Considering all I've seen on the RIOS (not much, >admitedly), I'd say it's more of a CISC that uses some of the things >that RISC people have found to be helpful to make fast chips. Let me get this straight: the chip's implementation is complex (although it is still basicly a load/store architecture, and looks a lot like any other "RISC" chip), therefore it is a Complex Instruction Set Computer? Wow. I'm impressed. What the hell are they teaching you people? -- Sean Eric Fagan | "I made the universe, but please don't blame me for it; sef@kithrup.COM | I had a bellyache at the time." -----------------+ -- The Turtle (Stephen King, _It_) Any opinions expressed are my own, and generally unpopular with others.