Xref: utzoo comp.unix.questions:30706 comp.unix.misc:1351 comp.unix.sysv386:7273
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From: jtice@arlo.UVic.CA (Jason W. Tice)
Subject:  RISC (Reduced Instruction-Set Chip) vs. CISC
Message-ID: <1991Apr24.224650.27937@sol.UVic.CA>
Summary:  HELP!!! Any info is appreciated!
Keywords: init run level
Sender: jason@softwords.bc.ca
Nntp-Posting-Host: arlo.uvic.ca
Organization: University of Victoria, Victoria, BC, Canada
Date: Wed, 24 Apr 91 22:46:50 GMT

Any information regarding the RISC and CISC chips would be greatly appreciated.

What does it do? 
what are it's parametres?
what is the difference between RISC and CISC ?
can you tell me where to look to find more information on them?

please mail any information on either/or both of the RISC and CISC
chips to 
		jason@softwords.bc.ca
		or
		jtice@arlo.uvic.ca

		thank-you.  I'll post what I learn!

Jason W. Tice
-- 
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/ "I didn't do it man!"  -- Bart Simpson             \/ jtice@lester.uvic.ca  \
\"I before E except after C." What a weird language. /\ jason@softwords.bc.ca /
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