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From: rbe@yrloc.ipsa.reuter.COM (Robert Bernecky)
Subject: Re: RISC (Reduced Instruction-Set Chip) vs. CISC
Message-ID: <1991Apr26.051121.16076@yrloc.ipsa.reuter.COM>
Keywords: init run level
Reply-To: rbe@yrloc.ipsa.reuter.COM (Robert Bernecky)
Organization: Snake Island Research Inc, Toronto
References: <1991Apr24.224650.27937@sol.UVic.CA>
Date: Fri, 26 Apr 91 05:11:21 GMT

In article <1991Apr24.224650.27937@sol.UVic.CA> jtice@arlo.UVic.CA (Jason W. Tice) writes:
>Any information regarding the RISC and CISC chips would be greatly appreciated.
>
>What does it do? 
>what are it's parametres?
>what is the difference between RISC and CISC ?
>can you tell me where to look to find more information on them?

Hennessy (of MIPS and Stanford) and Patteron have an EXCELLENT book
which covers this topic in enough detail that you too can become
a computer designer! (Of course, you may not end up being a very good one,
but that's a separate problem).

The book is: Computer Architecture: A Quantitative Approach.

It came out last year and should be available in any good university
textbook store. If not, grump. This book is THE one to read to
understand why RISC machines have an edge over traditional CISC
machines. 




Robert Bernecky      rbe@yrloc.ipsa.reuter.com  bernecky@itrchq.itrc.on.ca 
Snake Island Research Inc  (416) 368-6944   FAX: (416) 360-4694 
18 Fifth Street, Ward's Island
Toronto, Ontario M5J 2B9 
Canada